Data communication devices typically transmit and receive serial data that has been phase encoded. Phase encoded data includes the synchronization information (i.e., clock signal) encoded together with the data in a signal stream of pulses or frames. Because the clock and data information is combined, only a single transmission medium, for example, co-axial cable, twisted pair, or optic fiber, is required to transmit the information from point to point. A clock and data recovery circuit is typically used at the receiving end to recover the clock and data information from the phase encoded serial data. The clock and data recovery circuit is typically required to match the frequency of the recovered clock signal with that of the clock signal at the transmitting end to a minimized tolerance.
One type of prior art data and clock recovery circuit employs an analog phase locked loop ("APLL"). The bandwidth of the APLL is a function of the APLL circuit parameters. The bandwidth of the APLL also depends on external resistors and capacitors that determine the bandwidth. One disadvantage of the APLL is that these resistors and capacitors typically need to be adjusted during system manufacture in order to guarantee an acceptable tolerance for the bandwidth of the APLL. This typically significantly increases the manufacturing cost of the system. Another disadvantage is that the bandwidth of the APLL is also sensitive to process variations, temperature variations, and power supply variations.
Another type of prior art data and clock recovery circuit is described in U.S. Pat. No. 5,103,466, issued on Apr. 7, 1992, and entitled CMOS DIGITAL CLOCK AND DATA RECOVERY CIRCUIT. This digital clock and data recovery circuit employs a digital data recovery technique to recover the clock and data information from the phase encoded serial data. FIG. 1 shows the digital low-pass filter used in the technique in block diagram form.
Referring to FIG. 1, digital low pass filter 10 includes subtractors 11 and 13 and a programmable shifter 12. A D-type register 14 is connected to subtractor 13 and to a rounding logic 15. Rounding logic 15 is connected to the output of filter 10. Subtractor 11 subtracts the input of the filter from the output of the filter to generate an error value to shifter 12. Shifter 12 shifts the error value to the right. A control signal TAU.sub.-- CONTROL is used to control and vary the shift amount of the error value in order to generate an attenuated error. At the start of reception of a new data packet, the shift amount is varied in order to quickly lock onto the frequency of the input signal. The attenuated error is then applied to subtractor 13 at which the error is subtracted from the unrounded output of the filter to generate an updated filter output which is stored in D-type register 14. D-type register 14 then applies the updated filter output to rounding logic 15 to generate the output of filter 10. The performance of the digital low pass filter is independent of variations of process, temperature, and power supply. In addition, the performance of the digital low pass filter does not depend on external components. This, in turn, causes the bandwidth of the digital clock and data recovery circuit to be substantially stable.
Programmable shifter 12 allows the digital filter time constant to vary under exact conditions. This is unlike an analog filter the time constant of which is difficult to vary in a precise and Well controlled manner. This bandwidth stability of digital filter 10, however, causes a problem of selecting the optimum bandwidth for the filter. The digital filter is actually designed to be adjusted very coarsely through its programmable shifter. As is known, the time constant .tau. of programmable shifter 12 can be calculated by the following equation: ##EQU1## wherein T.sub.P is the reference clock period and S is an integer and represents the shift amount of shifter 12. Hence, the bandwidth (BW) of the filter 10 can be calculated by the following equation: ##EQU2##
In a Token Ring network, the reference clock period T.sub.P is typically 31.25 nanoseconds for a data transmission rate of 16 MBits per second. When this value of T.sub.P is substituted into equation 2, a number of bandwidths can be obtained from the equation, each corresponding to one of a number of shift amounts. FIG. 2 illustrates a table that tabulates these bandwidths in accordance with their respective shift amounts. As can be seen from FIG. 2, the bandwidth resolution is seen to be very coarse. The bandwidth difference .DELTA. between two adjacent bandwidths not only changes dramatically as a function of bandwidth, but also is larger than the bandwidth itself. Such behavior makes digital filter 10 of FIG. 1 typically unsuitable for a clock and data recovery circuit of a Token Ring network.